This document describes ValueRAM's 1G x 64-bit (8GB) DDR3-
1600 CL11 SDRAM (Synchronous DRAM) 2Rx8, memory
module, based on sixteen 512M x 8-bit FBGA components. The
SPD is programmed to JEDEC standard latency DDR3-1600
timing of 11-11-11 at 1.5V. This 240-pin DIMM uses gold
contact fingers. The electrical and mechanical specifications
are as follows:
• JEDEC standard 1.5V Power Supply
• VDDQ = 1.5V
• 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal banks
• Programmable CAS latency: 11, 10, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• 8-bit pre-fetch
• Burst Length: 8 (interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write (either on the fly using A12 or
MRS)
• Bi-directional Differential Data Strobe
• Internal (self) calibration: Internal self calibration through ZQ
pin (RZQ: 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°Cº
• Asynchronous Reset
• PCB: Height 0.740” (18.75mm) or 1.180” (30.00mm)
This document describes ValueRAM's 1G x 64-bit (8GB)
DDR3L-1600 CL11 SDRAM (Synchronous DRAM), 2Rx8,
low voltage, memory module, based on sixteen 512M x 8-bit
FBGA components. The SPD is programmed to JEDEC standard latency DDR3-1600 timing of 11-11-11 at 1.35V or 1.5V.
This 240-pin DIMM uses gold contact fingers. The electrical
and mechanical specifications are as follows:
• JEDEC standard 1.35V and 1.5V Power Supply
• VDDQ = 1.35V and 1.5V
• 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 11, 10, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
• Asynchronous Reset
• PCB: Height 0.740” (18.75mm) or 1.180” (30.00mm)
This document describes ValueRAM's 1G x 64-bit (8GB) DDR3-
1600 CL11 SDRAM (Synchronous DRAM) 2Rx8, memory
module, based on sixteen 512M x 8-bit FBGA components. The
SPD is programmed to JEDEC standard latency DDR3-1600
timing of 11-11-11 at 1.5V. This 240-pin DIMM uses gold
contact fingers. The electrical and mechanical specifications
are as follows:
• JEDEC standard 1.5V Power Supply
• VDDQ = 1.5V
• 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal banks
• Programmable CAS latency: 11, 10, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• 8-bit pre-fetch
• Burst Length: 8 (interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write (either on the fly using A12 or
MRS)
• Bi-directional Differential Data Strobe
• Internal (self) calibration: Internal self calibration through ZQ
pin (RZQ: 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°Cº
• Asynchronous Reset
• PCB: Height 0.740” (18.75mm) or 1.180” (30.00mm)
This document describes ValueRAM's 1G x 64-bit (8GB)
DDR3L-1600 CL11 SDRAM (Synchronous DRAM), 2Rx8,
low voltage, memory module, based on sixteen 512M x 8-bit
FBGA components. The SPD is programmed to JEDEC standard latency DDR3-1600 timing of 11-11-11 at 1.35V or 1.5V.
This 240-pin DIMM uses gold contact fingers. The electrical
and mechanical specifications are as follows:
• JEDEC standard 1.35V and 1.5V Power Supply
• VDDQ = 1.35V and 1.5V
• 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 11, 10, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
• Asynchronous Reset
• PCB: Height 0.740” (18.75mm) or 1.180” (30.00mm)
